Tensordyne
Staff ASIC STA Engineer
Sunnyvale, CA +1 · Staff · Full-time · Posted Oct 3, 2026
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 10+ years of hands-on ASIC engineering experience.
- Education
- Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
About the job
Lead hands-on ASIC physical static timing analysis (STA) design and workflow development, owning timing closure and signoff for multimodal generative AI inference chips.
What you'll do
- Own full-chip timing closure and signoff, including hierarchical STA, timing analysis, and clock analysis.
- Develop and improve ASIC timing optimization, implementation, and exploration workflows and technologies.
- Guide and support backend design teams on STA issues, clock trees, routing, and timing ECOs at block and full-chip levels.
What they ask for
- 10+ years of hands-on ASIC engineering experience, including deep knowledge of VLSI/SoC physical design workflows.
- Strong STA physical-design knowledge and ability to write SDCs for high-speed interfaces and multi-clock-domain blocks.
- Experience with clock methodology, hierarchical constraints, and leading or supporting backend design teams.
- Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
Tools
Cadence, Synopsys PrimeTime, Tempus, SDC, PCIe, SerDes, Genus, Innovus
AI focus
Develop STA design and engineering workflows for multimodal generative AI inference acceleration products in an environment that utilizes GenAI frontier models.
Model-written summary · the original posting is authoritative