Tenstorrent
DFT Engineer
$100K–$500K
Santa Clara, California, United States +1 · Full-time · Posted Jun 30, 2026
- Location
- Santa Clara, California, United States
Austin, Texas, United States - Experience
- 10+ years of relevant DFT experience.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; depending on citizenship/permanent residency status, prior license approval may be required. Offers may be rescinded if employment is not possible under U.S. export laws.
About the job
Implements and verifies design-for-test (DFT) for high-speed CPU cores and multi-chiplet System-in-Package designs, supporting manufacturing test and silicon debug.
What you'll do
- Build and execute chip-level DFT strategies for CPU and multi-chiplet designs.
- Implement and verify scan chains, memory BIST, and JTAG; support silicon debug and manufacturing test.
- Automate and analyze DFT flows, including ATPG and fault-coverage reporting, in collaboration with design teams.
What they ask for
- 10+ years of relevant DFT experience.
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Hands-on experience with industry-standard DFT tools such as Synopsys and Siemens, and scripting in TCL and Python.
- Expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of inserted DFT logic.
Pay
$100k - $500k (total pay; includes base and variable compensation targets)
Tools
Synopsys, Siemens, TCL, Python, ATPG, JTAG
Model-written summary · the original posting is authoritative