Tenstorrent
Formal Verification Engineer
$100K–$500K
Santa Clara, California, United States +3 · Full-time · Posted Oct 5, 2026
- Location
- Santa Clara, California, United States
Spain
Santa Clara, California, United States
Spain - Experience
- 6+ years in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology. Depending on citizenship/permanent residency status or ability to obtain prior license approval, an offer may be contingent or rescinded under U.S. export laws.
About the job
Prove the correctness of high-performance RISC-V CPUs and AI compute platforms using formal methods, partnering with architects and RTL designers to develop properties, analyze failures, and resolve issues.
What you'll do
- Develop properties and formal verification environments for complex hardware behavior.
- Analyze counterexamples and failures, debug RTL, and drive issues to closure.
- Collaborate with CPU architects, RTL designers, and other DV engineers to improve design correctness.
What they ask for
- Hands-on experience with formal verification methodologies and tools, including property checking, assertions, assumptions, constraints, and coverage analysis.
- Strong SystemVerilog skills, including writing and debugging SVA.
- Solid understanding of digital design and computer architecture.
- Strong programming and scripting skills in Python, Tcl, C/C++, or similar.
Nice to have
- Experience with CPU pipelines, caches, interfaces, control logic, or other complex microarchitecture is highly valuable.
Pay
$100k - $500k including base and variable compensation targets; total pay
Tools
RISC-V, SystemVerilog, SVA, Python, Tcl, C/C++
AI focus
Verifies CPUs and AI compute platforms intended for AI workloads; no direct AI model development is described.
Model-written summary · the original posting is authoritative