Tenstorrent
Front End Design Verification Engineer
$100K–$500K
Santa Clara, California, United States +3 · Full-time · Posted Sep 15, 2026
- Location
- Santa Clara, California, United States
Spain
Santa Clara, California, United States
Spain - Experience
- 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs; candidates at various experience levels are welcome.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; depending on citizenship/permanent residency status, employment may require prior license approval from the U.S. Commerce Department or an applicable federal agency.
About the job
Verify the instruction-fetch front end of a high-performance RISC-V CPU, developing tests, debugging failures, and ensuring correct behavior across workloads and corner cases.
What you'll do
- Develop verification strategies and testbenches for instruction fetch, prediction, decode, and dispatch.
- Create sophisticated tests and debug RTL and simulation failures.
- Work with CPU architects and RTL designers to verify CPU front-end correctness.
What they ask for
- Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
- Solid understanding of CPU architecture, including areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
- Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
- Strong programming skills in C/C++ and/or Python.
Pay
$100k - $500k (USD, including base and variable compensation targets; base salary and total pay split not specified)
Tools
SystemVerilog, UVM, C/C++, Python, RISC-V
Model-written summary · the original posting is authoritative