Tenstorrent
Full-Chip Physical Design Verification Engineer
$100K–$500K
Austin, Texas, United States +3 · Full-time · Posted May 1, 2026
- Location
- Austin, Texas, United States
Fort Collins, Colorado, United States
Santa Clara, California, United States
Santa Clara, California, United States - Experience
- 7–14 years; candidates at various experience levels are welcomed and assessed for an appropriate level.
- Education
- BS/MS in Electrical/Electronics Engineering or related field.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; some candidates may require prior U.S. Commerce Department or applicable federal agency license approval.
About the job
Drives full-chip physical verification signoff and tapeout closure to ensure manufacturable, high-quality SoCs across advanced process nodes.
What you'll do
- Lead physical verification closure, including DRC, LVS, ERC, and related checks; debug issues with industry-standard tools.
- Collaborate with RTL, PD, CAD, packaging, and foundry teams to achieve successful tapeouts.
- Develop and optimize verification flows and automation; provide technical leadership and mentoring.
What they ask for
- BS/MS in Electrical/Electronics Engineering or related field.
- 7–14 years of hands-on CPU/IP/SoC physical verification experience.
- Expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows.
- Background in ESD planning, padring integration, bump/RDL strategies, reliability analysis, advanced nodes, and FinFET design; proficiency in Python and TCL.
Pay
$100k - $500k USD total pay (including base and variable compensation targets)
Tools
Calibre, ICV, Pegasus, FC, Innovus, Python, TCL
Model-written summary · the original posting is authoritative