Tenstorrent
Midcore Design Verification Engineer
$100K–$500K
Santa Clara, California, United States +3 · Full-time · Posted Sep 16, 2026
- Location
- Santa Clara, California, United States
Spain
Santa Clara, California, United States
Spain - Experience
- 6+ years; candidates at various experience levels are welcome and assessed for an appropriate level.
- Visa sponsorship
- Offer is contingent on eligibility to access U.S. export-controlled technology; may depend on citizenship/permanent residency status or the ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
About the job
Verifies high-performance RISC-V CPU cores by developing verification strategies and test environments, debugging failures, and driving issues to closure.
What you'll do
- Develop test plans and architect test benches for CPU core verification.
- Debug RTL and simulation failures, identify root causes, and resolve issues with cross-functional teams.
- Verify complex processor behavior, including out-of-order execution and interacting subsystems.
What they ask for
- 6+ years of design verification experience for CPUs, SoCs, ASICs, or other complex digital designs.
- Strong SystemVerilog and UVM experience, including testbench development, constrained-random testing, assertions, and functional coverage.
- Understanding of CPU architecture and/or microarchitecture.
- Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools; strong C/C++ or Python skills.
Pay
$100k - $500k USD total pay (including base and variable compensation targets)
Tools
RISC-V, SystemVerilog, UVM, C/C++, Python, RTL
Model-written summary · the original posting is authoritative