Tenstorrent
Mixed Signal IC Layout Engineer
$100K–$500K
Santa Clara, California, United States · Full-time · Posted Sep 28, 2026
- Experience
- Typically ~10+ years in analog/mixed-signal layout; candidates at various experience levels are welcome.
- Education
- BSEE or equivalent experience.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; citizenship/permanent residency status or prior license approval may be required under U.S. export laws.
About the job
Design and verify full-custom analog and mixed-signal IC layouts for high-speed blocks and their integration into SoCs and a D2D PHY.
What you'll do
- Create manufacturable layouts from schematics and develop block- and top-level floorplans, placement, and routing.
- Optimize parasitics, coupling, IR drop, and electromigration to meet performance targets and close physical-verification checks.
- Support post-layout extraction and simulation; optionally contribute layout methodologies and automation scripts.
What they ask for
- Full-custom analog/mixed-signal layout experience, including high-speed blocks.
- Proficiency with Synopsys Custom Compiler or Cadence Virtuoso and Synopsys ICV or Siemens Calibre.
- Deep CMOS/FinFET experience, delivered silicon, and knowledge of EM/IR, ESD, and latch-up.
- Ability to own complex blocks and collaborate with circuit designers.
Nice to have
- Experience with TSMC or Samsung 12nm–2nm processes.
- Layout methodology or automation scripting experience (Python, Tcl, SKILL, etc.).
Pay
$100k - $500k (base and variable compensation targets; posting does not specify whether this is base salary or total pay).
Tools
Synopsys Custom Compiler, Cadence Virtuoso, Synopsys ICV, Siemens Calibre, Python, Tcl, SKILL, FinFET
Model-written summary · the original posting is authoritative