Tenstorrent
Physical Design Engineer, AI Accelerator IP
$100K–$500K
Austin, Texas, United States +5 · Full-time · Posted Aug 12, 2026
- Location
- Austin, Texas, United States
Belgrade, Serbia
Toronto, Ontario, Canada
Austin, Texas, United States
Belgrade, Serbia
Toronto, Ontario, Canada - Experience
- 5+ years of block-level or IP-centric physical design through tapeout.
- Education
- BS/MS/PhD in EE/ECE/CE/CS.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; depending on citizenship or permanent residency status, prior license approval may be required. Offers may be rescinded if employment is not possible under U.S. export laws.
About the job
Owns end-to-end physical implementation of RISC-V and AI accelerator IP, from synthesis through place-and-route, timing closure, and GDSII signoff.
What you'll do
- Implement IP blocks through tapeout and deliver PPA-proven collateral for customer integration.
- Work with RTL owners to close critical paths and meet power budgets.
- Build floorplans, power grids, pin placement, and clocking strategies; produce signoff deliverables.
What they ask for
- BS/MS/PhD in EE/ECE/CE/CS and 5+ years of block-level or IP-centric physical design through tapeout.
- Expertise with Innovus, ICC2/FusionCompiler, PrimeTime, and Tcl, Python, or Perl.
- Deep understanding of advanced-node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC).
- Experience with floorplanning, power grids, pin placement, clocking strategies, and IP integration collateral.
Pay
$100k - $500k (USD, total pay including base and variable compensation targets)
Tools
Innovus, ICC2/FusionCompiler, PrimeTime, Tcl, Python, Perl, UPF, LEF/DEF
AI focus
Physical implementation and delivery of AI accelerator IP.
Model-written summary · the original posting is authoritative