Tenstorrent
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
$100K–$500K
Santa Clara, California, United States · Full-time · Posted Feb 26, 2026
- Experience
- 5+ years; candidates at various experience levels are considered and assessed for an appropriate level.
- Education
- B.S./M.S. in EE/CE or related field.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; some applicants may need prior U.S. Commerce Department or applicable federal agency license approval, based on citizenship or permanent-residency status.
About the job
Leads physical implementation and sign-off of high-speed die-to-die interfaces, taking designs from RTL through GDSII and tapeout for multi-die and chiplet architectures.
What you'll do
- Own D2D physical implementation and closure, including synthesis, floorplanning, place-and-route, CTS, optimization, and sign-off.
- Drive STA, signal-integrity analysis, and DRC/LVS sign-off for high-speed designs.
- Improve physical-design flows and automation, and coordinate with chiplet, full-chip, and analog teams on integration and tapeout.
What they ask for
- 5+ years as an ASIC Physical Design Engineer at 7nm or below, with multiple successful tapeouts.
- Experience owning full-chip implementation from RTL to GDSII.
- Familiarity with high-speed interfaces and timing, signal-integrity, and power-integrity challenges.
- B.S./M.S. in EE/CE or a related field.
Pay
$100k - $500k including base and variable compensation targets (base and variable compensation; not separated into base salary and total pay).
Tools
Tcl, Python, Synopsys, Cadence, Mentor, LEF/LIB
Model-written summary · the original posting is authoritative