Tenstorrent
Physical Design Engineer, PnR
$100K–$500K
Austin, Texas, United States +3 · Full-time · Posted May 4, 2026
- Location
- Austin, Texas, United States
Fort Collins, Colorado, United States
Santa Clara, California, United States
Santa Clara, California, United States - Experience
- Various experience levels; no specific number of years stated.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; citizenship/permanent residency status or prior export-license approval may be required for some candidates.
About the job
Implement high-performance AI SoC partitions from synthesis through place-and-route, timing, and tapeout signoff.
What you'll do
- Execute synthesis, PNR, and STA for assigned partitions.
- Help close EM/IR, align UPF power intent with implementation, and drive LEC and physical verification signoff.
- Work with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
What they ask for
- Experience with synthesis and place-and-route flows.
- Experience using Synopsys Design Compiler / Fusion Compiler and IC Compiler II.
- Ability to own a block or subsystem and collaborate on tapeout milestones with clear communication and accountability.
Nice to have
- Depth in UPF/multi-voltage power domains, SoC interface IP integration, signoff, multi-clock/CDC-aware implementation, PLL/DLL integration, or DFT-aware physical implementation.
Pay
$100k - $500k (total pay, including base and variable compensation targets)
Tools
Synopsys Design Compiler, Fusion Compiler, IC Compiler II, UPF, I3C, UART, DRC/LVS, EM/IR
AI focus
Implements physical design partitions for an AI SoC.
Model-written summary · the original posting is authoritative