Tenstorrent
Sr. Staff Engineer, CPU (Front-End) Verification
$100K–$500K
Austin, Texas, United States +3 · Senior Staff · Full-time · Posted Sep 4, 2026
- Location
- Austin, Texas, United States
Santa Clara, California, United States
Austin, Texas, United States
Santa Clara, California, United States - Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; depending on citizenship or permanent residency status, or ability to obtain prior license approval, employment may not be possible.
About the job
Verify Tenstorrent’s RISC-V CPU front-end units by building testbenches, generating stimulus, and checking instruction fetch, branch prediction, and related structures.
What you'll do
- Build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
- Develop constrained-random and directed tests, plus C++ reference models and predictors for checking.
- Execute verification plans, track functional and code coverage, and verify edge cases.
What they ask for
- Background verifying CPU front-end blocks using SystemVerilog, UVM, and C++.
- Hands-on experience building unit-level testbench environments with precise stimulus and checking.
- Experience building reusable transactors, predictors, and scoreboards.
- Ability to collaborate with RTL designers to debug misspeculation, redirect, and fetch edge cases.
Pay
$100k - $500k total pay (including base and variable compensation targets)
Tools
SystemVerilog, UVM, C++, Verilator
Model-written summary · the original posting is authoritative