Tenstorrent
Sr. Staff Engineer, RTL Physical Implementation Lead
$100K–$500K
Austin, Texas, United States +2 · Senior Staff · Full-time · Posted May 22, 2026
- Location
- Austin, Texas, United States
Santa Clara, California, United States
Santa Clara, California, United States - Experience
- No specific years stated; candidates at various experience levels are welcome and assessed during interviews.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; depending on citizenship/permanent-residency status, prior license approval may be required.
About the job
Leads front-end physical implementation and PPA optimization for a high-performance RISC-V CPU and subsystem across process technologies.
What you'll do
- Own physical implementation and PPA definition; create initial floorplans and early area, power, and frequency estimates.
- Collaborate with microarchitects, RTL designers, and PD teams to optimize CPU configurations and improve physical design flows.
- Run physical design experiments, evaluate PPA trade-offs, and communicate recommendations to design teams.
What they ask for
- Expertise in physical design practices for PPA optimization and experience in high-performance physical design.
- Proficiency in RTL coding (Verilog/VHDL) and familiarity with simulation and power-analysis tools.
- Skills in synthesis, place-and-route tools, flows, and physical design methodology.
- Background in CPU micro-architecture.
Pay
$100k - $500k (USD), including base and variable compensation targets; base salary and total pay split not stated.
Tools
RISC-V, Verilog, VHDL
Model-written summary · the original posting is authoritative