Tenstorrent
Top Level Physical Design Engineer
$100K–$500K
Austin, Texas, United States +5 · Full-time · Posted Apr 16, 2026
- Location
- Austin, Texas, United States
Fort Collins, Colorado, United States
Santa Clara, California, United States
Austin, Texas, United States
Fort Collins, Colorado, United States
Santa Clara, California, United States - Experience
- 8+ years; the posting also welcomes candidates at various experience levels, who will be assessed for the appropriate level.
- Visa sponsorship
- Employment is contingent on eligibility to access U.S. export-controlled technology; some candidates may need prior U.S. Commerce Department or applicable federal agency license approval.
About the job
Drives top-level physical implementation and chip-level design closure for complex AI accelerator and CPU system-on-chip designs.
What you'll do
- Implement full-chip floorplans, power grids, and clock networks.
- Drive timing closure, EM/IR analysis, and physical verification at the chip level.
- Collaborate with architecture, RTL, and packaging teams on physical design.
What they ask for
- 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
- Expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
- Experience with bump planning, RDL implementation, and multi-voltage domain designs.
- Mastery of timing closure, EM/IR analysis, and chip-level physical verification.
Pay
$100k - $500k including base and variable compensation targets (base salary and variable compensation; no separate ranges stated)
Tools
RISC-V
AI focus
Physical design of AI accelerators and AI/CPU SoCs.
Model-written summary · the original posting is authoritative