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NPU Architect Engineer, Multimedia Lab
San Jose, California · Full-time · Posted Oct 31, 2026
- Education
- Master's degree or above in Microelectronics, Electronic Engineering, Integrated Circuits, Computer Science, or a related field.
About the job
Designs and optimizes NPU hardware architecture for next-generation chips, modeling AI inference performance and guiding module implementation and verification.
What you'll do
- Design, analyze, and optimize NPU module architecture and performance.
- Model emerging deep learning algorithms on chip systems and help define chip specifications, including throughput, bandwidth, and memory.
- Write architecture specifications and guide microarchitecture implementation, optimization, and verification.
What they ask for
- Master's degree or above in Microelectronics, Electronic Engineering, Integrated Circuits, Computer Science, or a related field.
- Familiarity with Tensor Core and relevant experience in hardware acceleration for large language models.
- Solid knowledge of computer architecture and digital integrated circuit design.
- Familiarity with deep learning algorithms and distributed frameworks for large language model inference, including how to compute chip inference performance.
Nice to have
- Tape-out experience.
- Experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms.
Tools
Tensor Core, Palladium, ZeBu, JasperGold, FPGA
AI focus
Performance modeling and analysis of deep learning algorithms, including large language model inference on chips; hardware-software co-optimization for real-world AI applications.
Model-written summary · the original posting is authoritative