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Senior SoC Digital Verification Engineer, Multimedia Lab

San Jose, California · Senior · Full-time · Posted Oct 28, 2026

Experience
3+ years of working experience in ASIC/SoC verification.
Education
Bachelor's degree or higher in Microelectronics, Computer Science, Electronic Communications, or a related field.

About the job

Develops and verifies video codec hardware accelerators, building verification plans and environments and driving simulation, coverage, and flow automation.

What you'll do

  • Create module-, subsystem-, and SoC-level verification plans and reusable UVM testbench environments.
  • Develop and run directed and constrained-random tests; close functional and code coverage, including gate-level and timing simulation.
  • Maintain regression automation and support FPGA prototyping and hardware/software debugging on emulation platforms.

What they ask for

  • Bachelor’s degree or higher in Microelectronics, Computer Science, Electronic Communications, or a related field.
  • 3+ years of working experience in ASIC/SoC verification.
  • Mastery of SystemVerilog and UVM, including independently building IP- or SoC-level verification environments.
  • Proficiency with mainstream simulation/debugging tools and Python/Perl/Shell scripting.

Nice to have

  • Familiarity with SoC subsystem architecture, protocols, and data flows; hardware emulation or FPGA prototyping experience.
  • Formal Verification experience or SoC-level Performance and Power-Aware (PA) verification experience.

Tools

SystemVerilog, UVM, VCS, Incisive, Questa, Verdi, Python, Perl

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)