AI Silicon, Junior Digital Design Engineer

What you'll do

• Define microarchitecture and integrate digital blocks and third-party IP into the SoC.
• Implement RTL and digital interfaces, targeting power, performance, and area goals; perform synthesis, timing, lint, CDC/RDC, and formal checks.
• Support block-level verification, debug simulation failures, and coordinate design handoffs to physical implementation.

What they ask for

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Expertise in Verilog RTL coding and digital design fundamentals.
• Familiarity with EDA tools for simulation, assertions, synthesis, linting, and CDC analysis.
• Understanding of the full ASIC design flow from specification to tape-out; excellent written and verbal communication skills.

Nice to have

• Experience with Machine Learning/Neural Network accelerator constraints or architectures, UVM, or formal verification.
• Exposure to post-silicon lab debugging, generative AI code development platforms, or integrating large analog mixed-signal blocks.

Tools

Verilog, SystemVerilog, EDA tools, UVM

AI focus

Design digital SoC components for an AI computing platform; accelerator-related design experience is a plus.