Unconventional AI
AI Silicon, Physical Design Engineer
Mountain View, CA I Remote +2 · Remote · Full-time · Posted Oct 1, 2026
- Location
- Mountain View, CA I Remote
Mountain View
Remote - Experience
- 10+ years of industry experience in digital physical design, with a track record of successful tapeouts.
- Education
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
About the job
Own the physical implementation and sign-off of high-performance, energy-efficient AI silicon, taking digital logic from RTL to GDSII.
What you'll do
- Lead physical design and top-level SoC integration, including floorplanning, power grid design, placement, clock tree synthesis, routing, and physical verification.
- Optimize power, performance, and area; collaborate with architects on timing closure and physical routability.
- Own sign-off and contribute to design-flow automation, analog integration, and evaluation of AI chip-design tools.
What they ask for
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs; understanding of advanced-node physical design challenges.
- Proficiency in power integrity analysis and noise coupling mitigation.
- Expert-level standard EDA tool-suite skills and scripting in Tcl, Python, or Perl; strong communication skills and experience managing external deliverables.
Nice to have
- Tapeout experience on 7nm, 5nm, or newer process nodes; experience with ML accelerators or large-scale systolic arrays.
- Experience with custom analog integration, multi-voltage domains, UPF/CPF, advanced power-gating, or AI tools for chip design.
Tools
RTL, GDSII, Static Timing Analysis (STA), Synopsys Fusion Compiler, IC Compiler II, Cadence Innovus, Tcl, Python
AI focus
Physical design for an AI computing platform; the role also evaluates AI tools that could improve chip-design efficiency.
Model-written summary · the original posting is authoritative