Upscale AI
ASIC Design - Principal Engineer
$250K–$265K
US - Santa Clara, CA · On-site · Principal · Full-time · Posted Aug 14, 2026
- Experience
- 5+ years of related technical engineering experience; 5+ years of industry experience in logic design on complex ASICs. Preferred: 12+ years of relevant industry experience.
- Education
- BE or MS in EE, CE, CS.
About the job
Design ASIC micro-architecture and RTL for next-generation designs, working with verification, physical design, and DFT teams to meet power, performance, and area goals.
What you'll do
- Define and document micro-architecture and develop logic design/RTL.
- Collaborate with verification and emulation teams on test plans, debugging, and coverage closure.
- Work with physical design and DFT teams on timing closure, area optimization, and DFT logic integration.
What they ask for
- BE or MS in EE, CE, CS.
- 5+ years of related technical engineering experience and 5+ years of industry experience in logic design on complex ASICs.
- Experience with SystemVerilog for logic design.
- Understanding of logic design, clock domain crossing, synthesis, and timing closure.
Nice to have
- 12+ years of relevant industry experience with successful tapeouts; experience with high-performance, low-latency networking ASICs is a plus.
- Scripting proficiency using Python or Perl; experience with LINT, CDC, or RDC tools.
Pay
USD 250,000–265,000 per-year-salary; base salary
Tools
SystemVerilog, Python, Perl, LINT, CDC, RDC
AI focus
Design ASICs for infrastructure powering AI workloads.
Model-written summary · the original posting is authoritative