Design Verification Engineer

What you'll do

• Develop verification environments, testbenches, plans, test cases, and reusable verification components for block- and system-level designs.
• Verify RTL using directed and constrained-random testing, assertions, formal techniques, functional coverage, and gate-level simulation; analyze coverage and debug issues.
• Improve verification workflows and infrastructure, including applying data analytics and AI-assisted techniques to test generation, regression analysis, coverage optimization, and debugging.

What they ask for

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of industry experience, or a Master's degree with 7+ years of relevant experience.
• Proven experience verifying complex ASIC designs at block and system levels.
• Strong proficiency with SystemVerilog and the Universal Verification Methodology (UVM).
• Experience with verification planning, functional coverage, assertion-based verification, constrained-random verification, and regression management.

Nice to have

• Domain knowledge of Ethernet, PCIe, and switch fabric architectures.
• Familiarity with data analytics, AI/ML-assisted verification techniques, or automation tools.

Pay

USD 212,000–246,000 per-year-salary (base salary)

Tools

SystemVerilog, Universal Verification Methodology (UVM), C, C++, Python, Ethernet, PCIe

AI focus

Applies data-driven analytics and AI-assisted techniques to test generation, regression analysis, coverage optimization, and debug productivity.