Upscale AI
Sr. Principal Engineer, Scale-Up (Switch Silicon & Traffic Management)
$263K–$284K
US - Santa Clara, CA · On-site · Principal · Full-time · Posted Oct 15, 2026
- Experience
- 15+ years; substantial stretch as a senior individual contributor.
About the job
Own validation and release sign-off for traffic-management and data-path features on a scale-up AI networking platform, from SAI/SDK programming through ASIC behavior.
What you'll do
- Set validation strategy, test plans, coverage, and release criteria; qualify lossless and congestion behavior under RoCEv2 and GPU collectives.
- Build validation frameworks and debug tools, and lead cross-stack root-cause analysis across software, SDK, model, silicon, and Linux.
- Mentor QA engineers, represent validation in design reviews, and support customer deployments and field issues.
What they ask for
- 15+ years in networking software, system validation, or ASIC/platform QA, including substantial time as a senior individual contributor.
- Hands-on expertise in traffic management, including PFC, scheduling, buffers, classification and marking, queueing, and ECN/WRED.
- Strong L2/L3 and ACL fundamentals, with experience in SAI, a switch SDK, or a NOS such as SONiC or FBOSS.
- Ownership of validation frameworks and automation; Python or Go at framework-review level, solid Linux and packet/counter debugging, and demonstrated mentoring and communication skills.
Nice to have
- Ethernet ASIC QA; RoCEv2, RDMA, DCB, PFC tuning, DCQCN, or NCCL/RCCL on AI or HPC fabrics.
- ASIC bring-up and pre-/post-silicon correlation; buffer sizing and congestion debugging; line-rate tools such as Ixia, Keysight, or Spirent.
Pay
USD 263,000–284,000 per year (base salary)
Tools
SAI, SONiC, FBOSS, Python, Go, Linux, RoCEv2, NCCL/RCCL
AI focus
Validate networking and traffic-management behavior for AI workloads, including RoCEv2 and GPU collectives such as NCCL/RCCL.
Model-written summary · the original posting is authoritative