Drimva

Velaura AI

Custom Circuit Design (Sr. Staff / Principal)

Bangalore +1 · On-site · Senior Staff · Full-time · Posted Jul 23, 2026

Location
Bangalore
Santa Clara, CA
Experience
10+ years in custom digital circuit design, standard cell development, or memory circuit design.

About the job

Leads the design and optimization of high-performance, low-power standard cell libraries and custom digital circuits for advanced AI and high-performance computing silicon.

What you'll do

  • Architect and design transistor-level circuits and arithmetic building blocks, optimizing performance, power, and area.
  • Verify circuit functionality, timing, power, variation, and reliability across process, voltage, and temperature corners; support library development through post-layout validation.
  • Drive design methodologies and automation, collaborate across engineering teams, and mentor engineers.

What they ask for

  • 10+ years of experience in custom digital circuit design, standard cell development, or memory circuit design.
  • Expertise in transistor-level CMOS design for advanced technology nodes, including FinFET and GAA.
  • Experience optimizing standard cell libraries and using circuit simulation tools such as HSPICE, PrimeSim XA, or Spectre.
  • Experience with parasitic extraction using StarRC or Quantus, statistical and reliability verification, and taking complex projects from concept through silicon.

Nice to have

  • Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.
  • Experience with standard cell characterization using Liberate or PrimeLib, including Liberty (.lib) generation and validation.

Tools

Cadence Virtuoso, StarRC, Quantus, HSPICE, PrimeSim XA, Spectre, Solido, Spectre FMC

AI focus

Designs custom circuits and standard cell libraries for AI and high-performance computing silicon; the company describes its compute technology as serving cloud, edge, and Physical AI.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 6, 2026 (UTC)