Velaura AI
Design Verification Engineer
$150K–$250K
Santa Clara, CA +2 · On-site · Full-time · Posted Jul 16, 2026
- Location
- Santa Clara, CA
Austin, TX
Boston, MA - Experience
- Experience verifying complex digital systems; no number of years specified.
About the job
Verifies Velaura’s Physical AI SoC, from individual hardware blocks through system-level HW/SW behavior, including performance, reliability, and safety.
What you'll do
- Develop verification strategies, plans, environments, coverage, assertions, checkers, and scoreboards for SoC blocks and systems.
- Perform HW/SW co-verification, emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug and root-cause analysis.
- Verify system performance and real-time behavior under representative workloads; investigate issues across hardware and software.
What they ask for
- Experience verifying complex digital systems and debugging complex system-level issues.
- Strong understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
- Experience with SystemVerilog, UVM, C/C++, assertions, and coverage-driven verification.
- Familiarity with formal verification techniques and tools; understanding of relevant memory, interconnect, processor, or accelerator architectures.
Nice to have
- Experience with one or more of ISO 26262, IEC 61508, IEC 61511, or ISO 13849.
- Experience with AI, machine learning, or edge AI hardware.
Pay
USD 150,000–250,000 (per-year-salary)
Tools
SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, FPGA
AI focus
Verification of a Physical AI SoC; the role also uses AI-assisted verification workflows to improve productivity, quality, and coverage.
Model-written summary · the original posting is authoritative