DFT Engineer (Architect / Manager / Sr. Manager)

What you'll do

• Define DFT architecture, strategy, and methodology, and lead implementation of scan, ATPG, memory and logic BIST, boundary scan, and related features.
• Own DFT execution from architecture and integration through verification, sign-off, silicon bring-up, and production ramp; drive test coverage, quality, and manufacturability.
• Lead and mentor DFT engineers and coordinate execution with design, validation, test, product engineering, and manufacturing teams.

What they ask for

• 15+ years of experience in DFT architecture, implementation, and sign-off for ASIC/SoC designs.
• Experience defining and leading DFT strategy for large-scale ASIC/SoC programs from concept through silicon production.
• Expertise in scan design and compression, ATPG, MBIST, LBIST, JTAG, boundary scan, IJTAG, test access architecture, and fault simulation.
• Experience leading DFT teams and cross-functional execution, including post-silicon debug, yield improvement, failure diagnosis, and production test support.

Nice to have

• Experience with advanced-node or high-volume production silicon; AI accelerators, high-performance compute, CPU, GPU, NoC, or complex SoC architectures.
• Experience with scripting or DFT automation, low-power test methodologies, or automotive/functional-safety standards such as ISO 26262.

Tools

ASIC/SoC, ATPG, MBIST, LBIST, JTAG, IJTAG, Tcl, Python

AI focus

DFT for next-generation AI and high-performance computing silicon, including AI accelerators and compute designs.