Velaura AI
Principal Packaging Engineer
$200K–$300K
Santa Clara, CA +3 · On-site · Principal · Full-time · Posted Jul 15, 2026
- Location
- Santa Clara, CA
Austin, TX
Bangalore
Boston, MA
About the job
Owns advanced package architecture and development for Velaura SoCs, from concept through production, coordinating design and manufacturing teams to optimize performance, cost, and manufacturability.
What you'll do
- Lead package architecture, design, bump planning, substrate definition, and production delivery.
- Co-optimize package, die, board, and system designs, including signal integrity, power integrity, thermal, mechanical, and reliability considerations.
- Select package technologies and collaborate with foundry, assembly, substrate, test, and manufacturing partners.
What they ask for
- Deep experience developing advanced semiconductor packages for high-performance SoCs.
- Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing.
- Experience co-optimizing package design with silicon, board, SI/PI, thermal, and mechanical teams.
- Hands-on experience with signal integrity, power integrity, thermal, and reliability considerations in advanced packages.
Nice to have
- Experience with chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.
- HBM integration and high-bandwidth memory package architecture.
Pay
USD 200,000–300,000 per year; base salary
Tools
SoCs, flip-chip, LPDDR, PCIe, Ethernet, OSAT, N3, N2
Model-written summary · the original posting is authoritative