Velaura AI
RTL Designer
$150K–$250K
Santa Clara, CA · On-site · Full-time · Posted Jul 15, 2026
- Experience
- No specific number of years stated; applicants at all experience levels are welcome.
About the job
Design and optimize RTL for Velaura’s Physical AI SoC, working across architecture, software, verification, and physical design to deliver high-performance, power-efficient production silicon.
What you'll do
- Design, implement, and optimize RTL for SoC components and infrastructure.
- Collaborate on microarchitecture, hardware/software interfaces, and system-level performance improvements.
- Partner with verification and physical design teams through the development cycle.
What they ask for
- Experience designing RTL for complex digital systems.
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
- Experience with Verilog/SystemVerilog and modern RTL design methodologies.
- Understanding of performance, power, and area tradeoffs, and familiarity with relevant memory, interconnect, or accelerator architectures.
Nice to have
- Experience with AI, machine learning, or edge AI hardware.
- Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
Pay
USD 150,000–250,000 (per-year-salary) (base salary)
Tools
Verilog, SystemVerilog, FPGA
AI focus
The role builds hardware for Physical AI systems and involves hardware/software co-design spanning AI workloads. AI-assisted development workflows are used to improve engineering productivity, quality, and design exploration.
Model-written summary · the original posting is authoritative