Velaura AI
RTL Engineer Memory Subsystem
$150K–$250K
Santa Clara, CA · On-site · Full-time · Posted Sep 16, 2026
About the job
Design and optimize RTL for Velaura’s SoC memory subsystem, integrating controllers and external PHYs to deliver high-performance, low-power memory for Physical AI workloads.
What you'll do
- Design and optimize memory-subsystem RTL, including controllers, fabric interfaces, and PHY integration.
- Drive memory-path performance and power improvements, analyze bottlenecks, and support timing closure and power management.
- Collaborate with software, verification, physical design, and memory IP/PHY teams through design and silicon bring-up.
What they ask for
- Hands-on RTL design and ownership of memory-subsystem blocks in complex digital systems.
- Experience integrating memory controllers with PHYs, including DFI, initialization, training, and bring-up.
- Strong knowledge of high-speed, low-power memory technologies and their protocols, timing, and power states.
- Expert-level Verilog and SystemVerilog skills; experience with RTL methodologies including lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent.
Nice to have
- Familiarity with AXI, CHI, or ACE and quality-of-service mechanisms.
- Experience with silicon bring-up, memory-path reliability features, low-power techniques, or memory-controller development.
Pay
USD 150,000–250,000 (per-year-salary) (base salary)
Tools
Verilog, SystemVerilog, DFI, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, HBM
AI focus
Build memory-subsystem hardware for Physical AI workloads; use AI-assisted engineering workflows to improve productivity, quality, and design exploration.
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