Velaura AI
RTL Power Engineer
$200K–$300K
Santa Clara, CA · On-site · Full-time · Posted Aug 19, 2026
- Education
- BS or higher in Electrical Engineering, Computer Engineering or a related field.
About the job
Design and own SoC power-management hardware, architecture, controls, and telemetry to meet performance, power, and thermal limits.
What you'll do
- Design power-management hardware and control loops for power, current, and temperature limits.
- Own clock/reset architecture and implement power-state management, including DVFS, retention, and low-power flows.
- Correlate power estimates across RTL, emulation, and silicon; build telemetry and coordinate with hardware, firmware, and software teams.
What they ask for
- Strong understanding of power, current, thermal behavior, voltage droop, di/dt, IR drop, and power delivery networks.
- Experience designing power-management hardware and clock/reset architecture.
- Working knowledge of Verilog or SystemVerilog and modern RTL design methodology; experience with power estimation and analysis from RTL through gate level.
- BS or higher in Electrical Engineering, Computer Engineering, or a related field.
Nice to have
- Experience with DVFS, adaptive voltage or clocking, droop detection, UPF, or silicon power correlation.
- Experience with thermal design, firmware or PMIC interfaces, power-analysis tools, robotics, edge AI, or AI-assisted design workflows.
Pay
USD 200,000–300,000 per year (base salary)
Tools
Verilog, SystemVerilog, UPF, PowerArtist, PrimePower, Joules, PMIC
AI focus
The role may use AI-assisted design workflows to improve productivity and design exploration.
Model-written summary · the original posting is authoritative