Senior Design Verification Engineer

What you'll do

• Develop verification strategies, environments, plans, coverage goals, assertions, checkers, and scoreboards for SoC components and systems.
• Verify hardware and HW/SW interactions, including performance and real-time behavior; participate in emulation, FPGA prototyping, and pre- and post-silicon debug.
• Collaborate across engineering teams and use AI-assisted verification workflows to improve productivity, quality, and coverage.

What they ask for

• 10+ years of experience verifying complex digital systems.
• Strong knowledge of computer architecture, microarchitecture, SoC architecture, digital design, low-power methodologies, CDC, clocking, and reset verification.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and formal verification techniques or tools.
• Experience with emulation, FPGA prototyping, or pre-silicon validation; ability to debug complex system-level issues.

Nice to have

• Experience with safety standards such as ISO 26262, IEC 61508, IEC 61511, or ISO 13849.
• Experience with AI or edge AI hardware, robotics or autonomous systems, real-time systems, or HW/SW co-verification.

Pay

USD 200,000–300,000 (per-year-salary)

Tools

SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, FPGA

AI focus

Verify a Physical AI SoC and use AI-assisted verification workflows to improve engineering productivity, quality, and coverage.