Velaura AI
Senior Emulation Engineer
$200K–$300K
Santa Clara, CA · On-site · Senior · Full-time · Posted Jul 24, 2026
- Experience
- 10+ years in hardware emulation and/or verification of complex digital systems.
About the job
Own and scale emulation infrastructure for a Physical AI SoC, enabling pre-silicon validation and HW/SW system bring-up.
What you'll do
- Set up, maintain, and optimize emulation flows and regression pipelines on Palladium, Veloce, and/or Zebu.
- Bring up designs and debug platform, compile, capacity, mapping, and system-level HW/SW issues.
- Support software co-verification and evaluate system performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
What they ask for
- Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu, including debugging compile and elaboration issues.
- Experience optimizing emulation regression flows; strong scripting and automation skills for build, regression, and CI pipelines.
- Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
- Strong grasp of computer, micro-, and SoC architecture, digital design fundamentals, and CDC, clocking, and reset behavior.
Nice to have
- Experience with FPGA prototyping, pre-silicon software bring-up, or HW/SW co-verification.
- Experience with AI, machine learning, or edge AI hardware, or using AI tools to accelerate engineering productivity.
Pay
USD 200,000–300,000 (per-year-salary)
Tools
Palladium, Veloce, Zebu, SystemVerilog, UVM, C/C++
AI focus
Apply AI-assisted verification and debug tools to improve engineering productivity, quality, and coverage; preferred experience includes AI, machine learning, or edge AI hardware.
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