Senior RTL Engineer

What you'll do

• Own RTL design, implementation, and optimization for significant SoC blocks, contributing to microarchitectural decisions.
• Collaborate across hardware, software, verification, and physical design teams on interfaces, system performance, and silicon delivery.
• Analyze bottlenecks and optimize for performance, power, area, scalability, and reliability; mentor junior engineers.

What they ask for

• 8+ years (or equivalent depth) designing RTL for complex digital systems, with significant block or subsystem ownership through tapeout.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert-level Verilog/SystemVerilog and modern RTL methodologies, including lint, CDC, synthesis-aware coding, and low-power intent.
• Experience with performance, power, and area tradeoffs, memory systems or accelerator architectures, and hardware/software co-design.

Nice to have

• Deep expertise in memory subsystems, DMA or data-movement logic, interconnect/coherency protocols, or NoC fabrics.
• Experience with AI or edge AI hardware, performance modeling, emulation, FPGA prototyping, silicon bring-up, or AI-assisted engineering workflows.

Pay

USD 200,000–300,000 (per-year-salary)

Tools

Verilog, SystemVerilog, LPDDR, DDR, HBM, AXI, CHI, ACE

AI focus

Contribute to a Physical AI SoC for intelligent physical systems, including AI workloads and potentially AI or edge AI hardware; use AI-assisted development workflows to improve engineering productivity and design exploration.