SoC Design Verification Engineer

What you'll do

• Plan and execute verification for assigned SoC areas, including boot, root of trust, clock and reset, low power, IO, and memory subsystems.
• Build and maintain SoC simulation environments and flows; run CDC and RDC analysis and verify latency, bandwidth, and QoS under representative workloads.
• Support coverage closure, SoC sign-off criteria, and tape-out readiness.

What they ask for

• 10 or more years in design verification, including significant SoC-level experience.
• Experience with multiple SoC verification projects, including sign-off and tape-out.
• SystemVerilog, UVM, C and C++, coverage-driven system-level verification, and simulation flows for ARM or RISC-V SoCs.
• Experience with PCIe and LPDDR5 or LPDDR6, boot and root of trust, system-level clock and reset verification, CDC/RDC tools, and UPF-based low-power verification.

Nice to have

• Depth in security, memory subsystem, interconnect, or power management; HW/SW co-verification; emulation or FPGA prototyping; or post-silicon bring-up and debug.
• Experience with functional safety standards, QoS or real-time systems, robotics or related fields, or AI-assisted verification workflows.

Pay

USD 200,000–300,000 per-year-salary; base salary

Tools

SystemVerilog, UVM, C, C++, ARM, RISC-V, PCIe, LPDDR5

AI focus

The role verifies a Physical AI SoC; AI-assisted verification workflows are a preferred experience.