Drimva

Velaura AI

SoC Design Verification Lead

$200K–$300K

Santa Clara, CA · On-site · Full-time · Posted Sep 15, 2026

Experience
12 or more years in design verification.

About the job

Leads system-level verification of Velaura’s Physical AI SoC, from verification planning and execution through sign-off and tape out.

What you'll do

  • Own the SoC verification strategy, architecture, environment, coverage goals, and sign-off execution.
  • Build and lead a verification team, providing technical direction while remaining hands-on.
  • Coordinate verification across boot and security, clock and reset, low power, IO and memory subsystems, and system software.

What they ask for

  • 12 or more years in design verification, including significant SoC-level experience.
  • Led SoC verification across multiple projects through sign-off and tape out, and built and led verification engineers.
  • Experience with SystemVerilog, UVM, C, C++, and coverage-driven system-level verification; CPU-based SoC simulation flows such as ARM or RISC-V.
  • Knowledge of IO and memory IP such as PCIe and LPDDR5 or LPDDR6; system-level verification of boot and root of trust, clock and reset, and low power, including CDC, RDC, and UPF flows.

Nice to have

  • HW/SW co-verification, pre-silicon software bring-up, emulation, or FPGA prototyping.
  • Experience with safety standards, QoS or real-time systems, post-silicon bring-up, early-stage team building, Physical AI domains, or AI-assisted verification.

Pay

USD 200,000–300,000 per year base salary

Tools

SystemVerilog, UVM, C, C++, ARM, RISC-V, PCIe, LPDDR5

AI focus

Verifies a Physical AI SoC for systems such as robots and autonomous machines; AI-assisted verification workflows are a preferred experience.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)