Sr Engineer CAD Pre-Silicon Front End

What you'll do

• Own front-end design and verification flows, including RTL checks, regression and coverage, and register-generation workflows.
• Build and bring up emulation and FPGA prototypes; maintain flow availability, tool versions, and issue turnaround.
• Deploy AI-assisted tools, improve engineering productivity, and coordinate front-end handoff with DFT and physical design.

What they ask for

• 8 or more years in design verification, design, or CAD engineering, including ownership of a flow area.
• Strong SystemVerilog and RTL fluency; hands-on experience building and running simulation and regression flows.
• Excellent Python skills and a track record of building maintainable tools for other engineers.
• Working knowledge of front-end EDA tools from Synopsys, Cadence, or Siemens EDA; Linux administration and distributed compute.

Nice to have

• Experience with UVM, cocotb, or Python-based verification; applying LLMs or agentic systems to engineering workflows.
• Experience taking an SoC from RTL bring-up through tapeout, or with emulation and FPGA prototyping platforms.

Pay

USD 200,000–300,000 (per-year-salary) — base salary

Tools

SystemVerilog, RTL, Python, Synopsys, Cadence, Siemens EDA, Linux, Grafana

AI focus

Build and deploy AI-assisted tooling across design and verification workflows; preferred experience includes applying LLMs or agentic systems, retrieval augmented generation, fine tuning, or code-model evaluation frameworks.