Voltai
CAD & Flow Methodology Engineer
Palo Alto Office · Full-time · Posted Oct 19, 2026
- Experience
- 5+ years of CAD, flow, or methodology experience at a semiconductor or EDA company.
About the job
Builds and maintains end-to-end chip design flows and infrastructure, integrating EDA tools with Voltai’s AI systems and data pipelines.
What you'll do
- Build and maintain flows across RTL, synthesis, STA, place and route, and signoff; develop regression, tracking, and reporting infrastructure.
- Integrate commercial EDA tools with AI agents and data pipelines, and partner with ML researchers to generate and curate design data.
- Manage EDA licenses, compute infrastructure, and job scheduling; support customer deployments in locked-down on-prem environments.
What they ask for
- 5+ years of CAD, flow, or methodology experience at a semiconductor or EDA company.
- Hands-on experience with major Synopsys and Cadence tools.
- Strong Python and Tcl, plus solid software engineering practices.
- Experience with LSF, Slurm, or similar compute farm infrastructure; understanding of the full RTL-to-GDSII flow.
Nice to have
- Experience with cloud or Kubernetes-based EDA infrastructure; open-source EDA tools (Yosys, OpenROAD).
- Background in ML data pipelines.
Tools
RTL, STA, Synopsys, Cadence, Python, Tcl, LSF, Slurm
AI focus
Integrate EDA tools with Voltai’s AI agents and data pipelines; partner with ML researchers to generate and curate design data.
Model-written summary · the original posting is authoritative