Voltai
Design for Test (DFT) Engineer
Palo Alto Office · Full-time · Posted Oct 19, 2026
- Experience
- 5+ years of DFT experience on production tapeouts.
About the job
Own DFT architecture and implementation for SoCs and IP, supporting silicon testing and helping develop AI-assisted DFT methods.
What you'll do
- Define DFT architecture and insert and verify DFT logic; generate ATPG patterns to meet coverage targets.
- Coordinate with RTL, synthesis, and physical design teams to close timing and area impact; support silicon bring-up, debug, and yield analysis.
- Automate DFT flows and coverage reporting, and help define AI applications for DFT insertion and pattern generation.
What they ask for
- Hands-on experience with Tessent, TestMAX, or Modus.
- Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
- Experience with DFT verification and gate-level simulation.
- Tcl and Python scripting.
Nice to have
- Post-silicon test bring-up and ATE experience.
- Experience with 2.5D/3D or chiplet test strategies; interest in AI-assisted design tools.
Tools
Tessent, TestMAX, Modus, Tcl, Python, IEEE 1149.1/1687
AI focus
Help AI learn DFT methodology and define how AI can accelerate DFT insertion and pattern generation.
Model-written summary · the original posting is authoritative