Voltai
Design Verification Engineer
Palo Alto Office · Full-time · Posted Nov 12, 2025
- Experience
- 4 to 6 years of hands-on verification experience.
About the job
Develop verification strategies and reusable tooling for chip IP and subsystems, incorporating AI-assisted workflows to improve verification, coverage, and debugging.
What you'll do
- Own verification from testbench architecture through signoff, including tapeout readiness, regression health, and coverage targets.
- Build reusable verification frameworks and AI-assisted workflows, integrating AI models into design verification environments.
- Collaborate with customers and cross-functional teams, shape product direction, and mentor junior engineers.
What they ask for
- Strong SystemVerilog and UVM skills with proven debugging depth.
- Familiarity with Python or similar scripting languages.
- Curiosity about AI or automation in verification.
- Ability to communicate and work across domains, including with software or ML teams.
Nice to have
- Experience with formal verification, co-simulation, or stimulus-generation frameworks.
- Background in ML, LLMs, data pipelines, tool development, or customer-facing engineering.
Tools
SystemVerilog, UVM, Python
AI focus
Design AI-assisted workflows for verification, coverage closure, and debugging; integrate AI models into existing design verification environments.
Model-written summary · the original posting is authoritative