Voltai
Low-Power Design Engineer
Palo Alto Office · Full-time · Posted Oct 19, 2026
- Experience
- 5+ years of low-power design or verification experience on production tapeouts.
About the job
Own power intent from architecture through signoff, designing and verifying low-power systems for silicon programs and helping train Voltai’s AI in power-aware design.
What you'll do
- Define SoC and IP power architecture and write UPF power intent; implement and verify power gating, clock gating, multi-voltage domains, and retention.
- Run power-aware simulation, static low-power checks, and CDC/RDC analysis; work with RTL, physical design, and signoff teams on power estimation and closure.
- Build automation for power analysis and reporting, and evaluate AI-generated power intent.
What they ask for
- Expert UPF knowledge and power-aware verification experience.
- Hands-on experience with tools such as VC LP, Conformal Low Power, or PowerArtist.
- Experience with CDC/RDC tools such as SpyGlass or Questa CDC, or similar.
- Python or Tcl scripting.
Nice to have
- Experience with mobile, edge, or data-center power management.
- Formal verification of power intent; interest in AI-assisted design tools.
Tools
UPF, VC LP, Conformal Low Power, PowerArtist, SpyGlass, Questa CDC, Python, Tcl
AI focus
Evaluate AI-generated power intent and help define correctness; help Voltai’s AI learn power-aware design.
Model-written summary · the original posting is authoritative