Voltai
RTL Design Engineer
Palo Alto Office · Full-time · Posted Oct 19, 2026
- Experience
- 5+ years of RTL design experience on chips that taped out.
About the job
Design and own production-silicon RTL while helping Voltai’s AI learn to write, review, and debug RTL.
What you'll do
- Own microarchitecture and SystemVerilog RTL implementation for IP blocks and subsystems; drive designs through lint, CDC/RDC, synthesis, and timing closure.
- Partner with verification and formal teams on test plans, assertions, and coverage; debug functional and timing issues across simulation, emulation, and silicon.
- Review AI-generated RTL, help define high-quality design, and work with customer design teams when needed.
What they ask for
- 5+ years of RTL design experience on chips that taped out.
- Expert SystemVerilog/Verilog skills and strong microarchitecture skills.
- Hands-on experience with lint, CDC, synthesis, and timing-aware design.
- Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar); Python or Tcl scripting.
Nice to have
- Experience writing SVA or working with formal verification; low-power design (UPF, clock and power gating).
- Interest in AI-assisted design tools.
Tools
SystemVerilog, Verilog, lint, CDC/RDC, synthesis, AXI, PCIe, Python
AI focus
Help Voltai’s AI learn to write, review, and debug RTL; review and evaluate AI-generated RTL.
Model-written summary · the original posting is authoritative