Voltai
Synthesis & Static Timing Analysis (STA) Engineer
Palo Alto Office · Full-time · Posted Oct 19, 2026
- Experience
- 5+ years of synthesis and STA experience on production tapeouts.
About the job
Owns synthesis and static timing analysis from RTL to a timing-clean netlist, while helping develop and evaluate AI for constraint writing, violation diagnosis, and timing closure.
What you'll do
- Develop SDC constraints, run logic synthesis, and drive timing closure across corners and modes.
- Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis; perform logic equivalence checking.
- Automate synthesis and timing flows and evaluate AI-generated constraints and timing fixes.
What they ask for
- Experience with synthesis and STA on production tapeouts.
- Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
- Strong SDC skills covering clocks, exceptions, generated clocks, and multi-mode constraints.
- Experience with logic equivalence checking (Formality or Conformal), plus Tcl and Python scripting.
Nice to have
- Advanced node experience (7nm and below).
- Experience with ECO flows and timing signoff methodology; interest in AI-assisted design tools.
Tools
RTL, SDC, Design Compiler/Fusion Compiler, Genus, PrimeTime, Tempus, Formality, Conformal
AI focus
Help Voltai's AI learn to write constraints, diagnose violations, and close timing; evaluate AI-generated constraints and timing fixes.
Model-written summary · the original posting is authoritative