Waymo
ASIC Design Verification Engineer
$175K–$215K
Mountain View, CA, USA +1 · Full-time · Posted Jun 10, 2026
- Location
- Mountain View, CA, USA
Mountain View, California, United States - Experience
- 3+ years building and maintaining complex testbenches using UVM/SystemVerilog.
About the job
Develop and improve verification plans, environments, and tests for custom silicon on Waymo’s autonomous-vehicle compute platform.
What you'll do
- Translate hardware specifications into scalable verification plans and build testbenches, reference models, and stimulus.
- Enhance reusable verification environments, integrate third-party Verification IP, and define functional and code coverage metrics.
- Promote verification best practices and analyze coverage to establish design readiness and closure.
What they ask for
- 3+ years building and maintaining complex testbenches using UVM/SystemVerilog.
- Experience with constrained-random generation, functional coverage, and SVA (SystemVerilog Assertions).
- Deep understanding of complex digital logic and debugging hardware/software interactions.
- Proficiency in Python for automation, data analysis, and regression management; strong communication and root-cause analysis skills.
Nice to have
- Experience from initial specification through post-silicon bring-up and validation; familiarity with UPF, formal verification, or hardware-software co-validation.
- Expertise in ML accelerators, NoCs, or high-bandwidth memory; C/C++; PCIe Gen 5/6, DDR5, or Ethernet; or Generative AI and LLMs for verification workflows.
Pay
$175,000 — $215,000 USD (base salary)
Tools
UVM, SystemVerilog, SVA (SystemVerilog Assertions), Python, UPF, C/C++, PCIe Gen 5/6, DDR5
AI focus
Preferred interest or experience using Generative AI and LLMs to accelerate verification workflows, such as automated testbench generation, documentation, or failure log analysis.
Model-written summary · the original posting is authoritative